Maximizing SoC Bandwidth using Dynamic Voltage and Frequency Scaling in 2021 CSIA ICCAD
Abstract:
As feature length scaling in advanced CMOS process nodes approaches both economic and physical limits, demand is increasing for improved design methods to support the need for more functionality with fixed power and area budgets. Dynamic Voltage and Frequency Scaling (“DVFS”) is one such method, which can help to ensure every chip can operate at the maximum possible speed for the process corner it was fabricated at, regardless of supply voltage level noise and operating temperature.
Silicon Creations provides modern clocking solutions in the world’s most advanced processes from 3nm to 180nm, which enable SoC designers to maximize logic speed and design functionality while minimizing risk and yield loss in high-volume production.
This paper introduces Silicon Creations fast-frequency-hopping clock Generator (“FG”) and Delay-to-Digital converter (“DDC”) silicon IP products, along with some typical performance metrics and applications. Various case studies are described, including the implementation of a clock speed control loop to maintain a constant average supply current in the presence of large variations in logic gate activity. Also, initial characterization and background calibration options are described to ensure each individual chip is calibrated to operate at the maximum speed in any environment.
Silicon Creations’ Frequency Generator and Delay-to-Digital converter are silicon-proven in TSMC 5nm FinFET and are currently being ported to other advanced process nodes including TSMC 3nm. We are ready to provide a low-risk solution for almost any clock your next SoC needs so you can spend your energy worrying about other parts of your design.
Biography– Chung-Chun (CC) Chen
has been with Silicon Creations since 2011 and is a principal circuit architect for the SerDes IO interface. Currently, CC leads the SerDes team as a Director of Analog/Mixed-Signal Design at Silicon Creations in Atlanta, Georgia. Before joining Silicon Creations, he was a research staff member at Samsung Electro-Mechanics design center in Atlanta, Georgia, and he was a principal engineer at TSMC in Hsinchu, Taiwan, where he worked on clocking architecture design and related customer support.
Chung-Chun (CC) Chen (S’02–M’09–SM’17) was born in Taipei, Taiwan, in 1979. He received a B.S. degree in the Institute of Electrical and Control Engineering at National Chiao Tung University, Hsinchu, Taiwan, in 2002, M.S. and Ph.D. degrees in Communication Engineering and Electrical Engineering from National Taiwan University, Taipei, Taiwan, in 2004, and 2009, respectively. His current research interests focus on circuit designs in clocking and other SerDes building blocks for high-speed communication systems. He has published over 15 papers in peer-reviewed conferences and journals. He is a Senior Member of the IEEE and served as a reviewer of JSSC and T-MTT.