soc lab

[SoC Design Lab - NYCU] Final Project - Group 11

SOC Clock Part II - Advanced SOC Design 2024 04 17

IC Testing - Boundary Scan - Advanced SOC Design 2024 03 28

Lab4 - Caravel-FSIC FPGA - Advanced SOC Design 2024 04 10

SOC - IO Part I - Advanced SOC Design 2024 05 08 09 10 GMT+8

AXI Bus Optimization

SOC Clock Part I - Advanced SOC Design 2024 04 17

Advanced Verification - Low power UPF Advanced SOC Design 2024 06 06

IC Testing - Scan Test - Advanced SOC Design 2024 03 27

SOC - Power - Advanced SOC Design 2024 05 09

Advanced STA - OCV/AOCV/POCV/AWP Advanced SOC Design 2024 05 29

Low Power Design - Power Basics : Advanced SOC Design 2024 04 10

IC Testing - Iddq Testing - Advanced SOC Design 2024 03 28

Advanced STA - Special Circuit Analysis - Advanced SOC Design 2024 05 30

AXI Bus Introduction

Low Power Design - Dynamic Power Reduction - Advanced SOC Design 2024 04 11

SOC - Reset - Advanced SOC Design 2024 04 18

Advanced STA - Crosstalk Part I - Advanced SOC Design 2024 05 29

Advanced Verification: Simulation Coverage - Advanced SOC Design 2024 06 05

SOC - IO Part II - Advanced SOC Design 2024 05 08

Low Power Design - Static Power Reduction - Advanced SOC Design 2024 04 10

Serdes - Advanced SOC Design 2024 05 23

Advanced STA - Path-based Analysis - Advanced SOC Design 2024 05 29

UserDMA Explained - Advanced SOC Design 2024 05 23