Low Power Design - Dynamic Power Reduction - Advanced SOC Design 2024 04 11
Logic Gate Optimization based on Switching Activity
Logic Restructure
Input Reorder
Glitch Elimination – balance delay
Precomputation
Algorithmic Level Techniques
VDD Reduction
Multi-VDD
Level-Shifter Handling
Clock Timing cross voltage domain
Clock Gating
Dynamic Voltage Frequency Scaling (DVFS)
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