Intel® Quartus® Prime Pro Software Timing Analysis – Part 5: Timing Exceptions
This is part 5 of a 5 part course. You will learn about and how to apply the timing exceptions false paths, multicycle paths, and min and max delays using the Synopsys* Design Constraints (SDC) format in the Timing Analyzer in the Intel® Quartus® Prime Pro software v. 20.3.
Note: While the focus of this course is the Intel Quartus Prime Pro software, much of the flow and constraints are valid with the Subscription and Lite versions of the software.