428 тысяч подписчиков
312 видео
Get Started Now with Agilex 5 for Intelligence Embedded Applications
CEO of Intel®, Pat Gelsinger, addresses the FPGA Community
Agilex™ 5 TinyML Demo with FPGA AI Suite
Intel Agilex® 5 FPGAs Hard-Processor SubSystem (HPS) Overview
Read Me First!
Creating a System Design with Platform Designer: Getting Started
Converting a Zynq*-7000 / Zynq UltraScale+* MPSoC Design to Agilex™ 5
Timing Analyzer: Required SDC Constraints
Understanding Timing Analysis in FPGAs
Session: FPGA AI Suite in Action
Intel® Agilex FPGA Configuration
Session: Secure Every FPGA for the Intelligent and Quantum Future
Altera Innovators Day 2025
Cyclone® V to Intel Agilex® 5 FPGA Migration
Reset Methodology
Altera 2025 Recap - Reflecting on a Transformative Year at Altera
AI-based Image Classification Using Agilex 5 FPGA
HLS Walkthrough Part 1: Creating an IP Component
We are Altera. We are for the innovators.
External Memory Interface Device Selector Tutorial
FPGA Security - Authentication and bitstream encryption tutorial
Using FPGAs with the Intel® oneAPI Toolkits
Reducing Compile Time with Fast Preservation
Intel® FPGA MACsec IP Tutorial 1
Intel® Quartus® Prime Software Ask an Expert April 25, 2022
Session: Integrate AI Into Your FPGA Design Quickly
Memory Subsystem IP for Intel Agilex® 7 F-Series and I-Series
Agilex™ 3 FPGA and SoC C-Series Development Kit
Intel® Agilex™ 5 FPGA Family Overview Video
Agilex™ 5 FPGAs In-Action External Memory Interfaces IP Demo Video
New Intel® Agilex™ D-series FPGAs
Unboxing the Agilex™ 5 FPGA E-Series 065B Premium Development Kit
Designing Boards with Intel® Agilex™ FPGAs
Introduction to Intel® Open FPGA Stack
Migrating to the Intel® Quartus® Prime Pro Edition Software
最新インテル® Agilex™ D シリーズ FPGA
Clock Domain Crossing Considerations
Introduction to Hyper-Optimization
Using Linux with Intel® SoC FPGAs "Ask an Expert" October 26, 2022
Arm® Development Studio for Intel® SoC FPGAs "Ask an Expert" September 29, 2022
Overview of Altera’s FPGA AI Suite Software
Signal Tap Logic Analyzer: Data Acquisition & Additional Features
HLS Walkthrough Part 3: Demo with Development Board
Nios®V Software Development Flow with Ashling* RiscFree* IDE for Intel® FPGAs
Intel® FPGA AI Suite "Ask an Expert" July 27, 2023
Verilog HDL Basics
Getting Started with Linux*OS for Altera® SoC FPGAs
Intel® Agilex™ FPGA CXL IP
Demo: 3rd Party Board and SOM Solutions Powered by Altera FPGA
Intel Agilex® 3 FPGA and SoC FPGA
