Simulation, Synthesis and Design methodology in Verilog | #4 | Verilog in Hindi
Join our Telegram group for more discussion and get some outstanding materials for exams and interviews along with job/internship openings update : https://t.me/joinchat/9q2ZFEfADY5lZWVl
#vlsipoint #verilog #HDL #RTL #verilog_in_hindi #simulation #synthesis
#complete_verilog_course #what_is_simulation #what_is_synthesis #verilog_design_methodology
Simulation is used to verify the functionality of the digital design that is modeled using HDL like Verilog.For simulation purpose we apply different input stimulus to the design at different time, to check whether the RTL code behaves in intended way or not.
Synthesis is a process in which the digital design that is modeled using HDL is translated into an implementation consisting logic gates.It will just make an optimal design based on the working strategy which we are using and also give the consumption of resources as available
Reference- verilog HDL : A Guide to Digital Design and Synthesis
By Samir palnitkar