Creating input and output delay constraints

AXI-Stream Arbiter example

Collaboration with Robert Feranec and new open source SystemVerilog toolbox

The Critical FPGA Basics: Always blocks, Inferred latches, and why the FPGA needs a clock, anyway?!

More Ethernet coding live, this time a testbench!

My first live! Started as a coding example, evolved into answering comments!

5000 Subscribers! Answering your frequently-asked questions!

Free FPGA resources short (see channel for longer video!)

Free FPGA training and resources!

Zynq Part 3: Combining my own HDL with the Vivado block diagram!

ILA in a Zynq: View signals in hardware!

Zynq Part 2: Zynq Vitis Example with PL Fabric GPIO and BRAM

Zynq Part 1: Vivado block diagram (no Verilog/VHDL necessary!)

Is chatGPT going to take my job? How well can chatGPT write Verilog?

AXI Part 3: AXI-Lite testbench (briefly)

AXI Introduction Part 2: AXI-Lite state machine example explained!

AXI Introduction Part 1: How AXI works and AXI-Lite transaction example

Reading from and writing to file: My PDM testbench from start to finish.

When and how to use the Multiplier IP core

FPGA Audio to my PC over Ethernet! PDM Microphone and CIC filter explained!

Receiving packets over Ethernet using Python

Handling Ethernet FIFO overflows in SystemVerilog! How to keep packets intact above line rate!

How to use the clocking wizard IP: creating a 50Mhz clock from 100Mhz

A quick and easy Ethernet Frame state machine, explained from start to finish!

Digilent Nexys A7-100T Review!