9 тысяч подписчиков
48 видео
Tips for Verilog beginners from a Professional FPGA Engineer
Setting up a Nexys board in Linux!
Fixing failed timing, a practical example in verilog!
AXI Stream basics for beginners! A Stream FIFO example in Verilog.
Generate statement and for loop example in Verilog: A byte-swap in three ways.
Zynq Part 2: Zynq Vitis Example with PL Fabric GPIO and BRAM
Timing report and RTL schematic interpretation
5000 Subscribers! Answering your frequently-asked questions!
FPGA unboxing and chat: Why I started this channel and future plans!
How much combinitorial logic is too much? Always block guide for beginners by FPGA professional.
6 Do's and don'ts for good Verilog coding practices
Polynomial example part 2! Final window code with pipelining!
Tips for working on a engineering design team as an intern or new graduate!
Creating input and output delay constraints
Timing Constraints: How do I connect my top level source signals to pins on my FPGA?
Collaboration with Robert Feranec and new open source SystemVerilog toolbox
FPGA Audio to my PC over Ethernet! PDM Microphone and CIC filter explained!
ILA in a Zynq: View signals in hardware!
When and how to use the Multiplier IP core
10 tips for writing a clear state machine in Verilog: A UART transmitter example.
Is chatGPT going to take my job? How well can chatGPT write Verilog?
FPGA Clock and timing concepts explained simply for beginners using two analogies!
Fixed point basics in Verilog for Beginners! Continuation of polynomial example.
How do I write to file? Testbench basics for beginners in Verilog!
Zynq Part 1: Vivado block diagram (no Verilog/VHDL necessary!)
Free FPGA resources short (see channel for longer video!)
AXI Part 3: AXI-Lite testbench (briefly)
My Linux + Vivado development environment!
A quick and easy Ethernet Frame state machine, explained from start to finish!
Vivado IP generator tricks: Generating IP, saving to version control, and generating example code!
Flashing a LED with Vivado and a Nexys A7 FPGA board: Step by step walkthrough!
My first live! Started as a coding example, evolved into answering comments!
Free FPGA training and resources!
AXI Introduction Part 2: AXI-Lite state machine example explained!
Zynq Part 3: Combining my own HDL with the Vivado block diagram!
Reading from and writing to file: My PDM testbench from start to finish.
Digilent Nexys A7-100T Review!
The Critical FPGA Basics: Always blocks, Inferred latches, and why the FPGA needs a clock, anyway?!
AXI-Stream Arbiter example
AXI Introduction Part 1: How AXI works and AXI-Lite transaction example
