Understanding Microarchitecture
Join us as Casey Muratori takes us through a look at some interesting topic areas around Performance Metrics through the use of Time Stamp Counters (TSC) and how code execution takes place inside the processor cores through the instruction cycle. When getting into low-level & hardware security and vulnerability research, these types of topics are key to gaining a proper understanding. We'll aim to turn this into a short series for a more holistic view.
Casey's Info:
https://www.computerenhance.com/
https://github.com/cmuratori
https://x.com/cmuratori
/ @caseymuratori