This project uses the opensource FPGA board, ULX3S, to implement a pipelined Sobel Edge Detection. Camera used here is the OV7670 camera and is displayed to monitor via HDMI.
The design is available as verilog files which can be synthesized to ULX3S FPGA board via the opensource FPGA tools(yosys+nextpnr+fujprog). The design is also available as an Icestudio file as shown on this video.
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Source code repo:
https://github.com/AngeloJacobo/ULX3S...
Camera Streaming with ULX3S FPGA Board and Icestudio: • Camera Streaming with ULX3S FPGA Board and...
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