This video will take you through Logical Fault insertion and Detection using Modelsim. The stuck at faults are injected in the gate level circuits using AND and OR gate and they are tested by applying test vectors. Finally an analysis is being made to find how many test vectors detects a single fault and in tern how many faults does a single test vector detects.
#Logical Fault insertion and Detection
Logical Fault Simulation
#VLSI Testing and Testability
Fault Coverage
Stuck at Faults simulation
Test Vector generation