FPGA Mario
In DT385, Advanced CG 2: Graphics Hardware, 3rd year students learn how to design 2D graphics processing unit on Basys3 FPGA using Verilog.
The main functions are comparable to the PPU on NES and SNES system. However, the hardware design are quite different from Nintendo's systems. The original game ROM would not run on our design.
The game logic is done via hardware state machine (no softcore CPU)
Spec:
640x480 pixel, 12-bit color, 60fps
2 background layers parallax scrolling
256 background tiles, 256 sprites tiles
tiles size 16x16, 32x32
64 sprites per line, per game
Basys3 utilization: BRAM 80%, LUT 10%
use double line buffer (not enough BRAM for a framebuffer)