Hi, I'm Stacey, and in this video I talk about writing a testbench in verilog!
Subreddit:
/ hdlforbeginners
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https://forms.gle/ssNwzTKiioj3RNHD9
Ending music: Faith by David van Niekerk
• Faith (Ocean of Reverb Original) - David v...
I'm on discord on the r/fpga server ( / discord , as Stacey, come say hi and chat all things FPGA!
0:00 Intro
0:26 Why we need a testbench
1:35 Clock Generation
1:51 Delays in simulation
3:00 Initial vs Always block
3:14 Reset Generation
3:58 Tripod Malfunction
4:15 Writing to file Module Start
5:24 Opening File
5:52 Casting data to Floating Point
6:43 Minor Fixed Point Detour
7:29 Writing to File
7:52 Summary
8:04 I have a subreddit!
8:33 Outro
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