Relationship Between TIE and Phase Noise

Опубликовано: 30 Май 2026
на канале: Microchip Developer Help
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See the rest of the series on this subject:    • Clocks & Timing Tutorials  

The video explains the relationship between Time Interval Error (TIE) and Phase Noise plots, illustrating how phase noise at specific frequency offsets represents the combined phase power of clock edges. It also discusses how spurs in the plot indicate deterministic phase noise sources, using an example of crosstalk between two clocks to show a significant phase noise increase at a particular frequency offset.