If your s-parameter graphs have unexpected discontinuities - this brief note tells you how to check for aliasing.
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Anatomy of pcb impedance testing with Polar CITS
Auto generate PCB impedance coupons with Speedstack & CGen
How to create impedance coupons with Polar Si8000m and CGen
Spotting and solving alias effects in s-parameters
Filtering PCB base materials in Speedstack
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Structure view simplifies management of layer stack design for PCBs with many transmission lines.
Separating dc resistance from PCB trace characteristic impedance measurement.
PCB fine line impedance - enhance correlation with field solver models
Si9000e Graph Goalseek Gradient - Graph impedance and insertion loss sensitivity.
CITS880s Setup Wizard
Drivers for PCB insertion loss - especially for viewers who do not have an electronics background