12~1: Logic implementation using Multiplexers

Tag, Index, Offset Bits Cache mapping

2 way Set Associative with block size 4 byte

L293D, DC motor and Arduino - Tinkercad simulation

20: Frequency Divider | Synchronous Counters | Asynchronous Counters

19~1: Deriving JK Latch Characteristic Table | JK Latch to Flip Flop conversion

20~2 Frequency Divider with JK Flip Flop

20~1: Asynchronous Counter | 4 bit Synchronous Counter

19: Latches to Flip Flops - Waveforms, JK, T, SR, D Flip Flops

21: Up / Down counter with control input - Sequential Circuit Design

18~2: D latch with Enable and Waveforms

18~1 :SR NOR latch with Enable E

18~0: SR NAND Latch (Basic design working)

17: BCD adder design

16: 4-bit Magnitude Comparator

15~0: Code converter~ Binary to Gray Code

15~1: BCD to 7 segment display Design Basics

BCD to 7 Segment Decoder ~ Design basics

Quiz 02: Solution DLD

14: De-Multiplexer Design~ Logic implementation with De-MUX

13: Encoders and Priority encoders

12~1: Logic implementation using Multiplexers

12~0: Design 16 by 1 MUX using 4 by 1 MUXs

11~2: Get 4 by 1 MUX functionality using 2 by 1 MUXs

11: Logic implementation via Decoders and Multiplexers ?