AND Gate verilog simulation using Modelsim
In this video, we demonstrate how to write, compile, and simulate a 2-input AND Gate using Verilog HDL in ModelSim.
This is a fundamental experiment for Digital Logic Design, VLSI Design, and FPGA programming learners.
🧠 What You’ll Learn
Writing Verilog code for a 2-input AND gate
Creating a testbench for simulation
Compiling and running the simulation in ModelSim
Viewing waveforms and verifying logical operation
💻 Verilog Code
// AND Gate
module andgate(a, b, c);
input a, b;
output c;
assign c = a & b;
endmodule
Steps in ModelSim
Create a new project
Add the andgate.v and andgate_tb.v files
Compile both modules
Run simulation for the testbench
Add signals to waveform and observe output