I2C - Bus Master - Step 4
Step 4 of the I2C Bus Master in Verilog project. This step introduces uses Xilinx's core generator to create a FIFO, and then we use a layered module approach to integrate the existing hardware with the FIFO buffer.
Step 4 of the I2C Bus Master in Verilog project. This step introduces uses Xilinx's core generator to create a FIFO, and then we use a layered module approach to integrate the existing hardware with the FIFO buffer.