Polynomial example part 2! Final window code with pipelining!
Hi, I'm Stacey, and in this video I go through my final window code, with pipelining! This is part 2 after the polynomial example algorithm prep video!
Original Algorithm Prep: • Algorithm preparation for the FPGA: A...
Fixed point explanation: • Fixed point basics in Verilog for Beg...
Practical timing example: • Fixing failed timing, a practical exa...
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Ending music: • Faith (Ocean of Reverb Original) - Da...
0:00 Intro
0:46 Use of SystemVerilog
1:32 Parameters
2:10 Negative bitslicing
2:30 Pipelining signal declarations
3:25 Alternate signal declaration option
4:12 Triangle Gen: Explanation
5:13 Triangle Gen: How it acts as a framework
5:51 Triangle Gen: Casting to fixed point
6:34 b calculation
7:09 b2 calculation and registers
7:27 Pipelining explanation
8:20 _q suffix explanation
8:43 _q suffix rules
9:28 b3 calculation
9:38 Pipeline diagram
10:52 Mapping pipelining diagram to code
11:40 Scaling stage
13:15 Adding to produce final 2 cases
13:36 Final mux
14:08 Simulation Results
14:44 Timing note 1
15:08 Timing note 2
15:30 Housekeeping
15:54 Outro