Binary parallel adder/ 4 bit parallel adder logic circuit design with full adders

Binary parallel adder/ 4 bit parallel adder logic circuit design with full adders

Half subtractor and Full subtractor logic circuit || Design of full subtractor with half subtractors

Calculating gain(K) for given gain or phase margin using calculator only without bode plot

How to use scientific calculator to calculate gain and phase margin without plotting bode plot.

How to plot bode plot with and without time delay and calculate gain and phase margin

Bode plot for stability analysis of control system and finding Gain and Phase Margin.

Exploring Root Locus Plots: Complex Poles and Multiple Pole Scenarios | Control System Analysis

Full Adder logic design with NOR gates only

Full Adder logic design with NAND gates only

Half Adder design with NOR gate only

Half Adder design with NAND gates only

Full Adder introduction / logic circuit design / design of full adder with half adders

Root locus sketch with 3 poles and finding stability condition.

How to plot root locus to find out stability of the control systems? Step-by-step process

Example of block diagram reduction technique in control system

Half adder / definition , truth table and circuit design

Combinational logic circuits/ Difference between combinational and sequential circuits/ design steps

Simplifying Control Systems: Block Diagram Reduction in 15 Minutes | Techniques & Rules Explained

How to solve source free series/ parallel RLC circuit explained under 7 minutes

Routh-hurwitz criteria |Examples and special cases of for stability test of the closed loop system|

Application of Laplace transform for solving circuit problems with example.

Example of Inverse Laplace's Transform for repeated poles using residual method

Inverse Laplace's transform by using decomposition and applying residual method.

Inverse Laplace transform of decomposed functions.