Xilinx Platform Studio - Setup Base System Builder for XUPV5 Board
This demonstrates creating a Xilinx Platform Studio (EDK) project for the XUPV5 board. I will walk through each of the steps in the BSB wizard. I will also show how to enable parallel synthesis, disable timing warnings as errors, how to add additional IP cores to a design, and how to edit the user constraints.
Notice: in the video, when editing the UCF file, I show "
Net xps_iic_0_Scl_pin LOC = U27;
Net xps_iic_0_Sda_pin LOC = T29;"
The correct line should be: "
Net xps_iic_0_Scl_pin LOC = U27 | IOSTANDARD = LVCMOS18;
Net xps_iic_0_Sda_pin LOC = T29 | IOSTANDARD = LVCMOS18;"
This corrects a conflict with the DRAM controller, which is using a 1.8V io standard. Since U27 and T29 are physically connected to the same I/O bank, they must share the same voltage restrictions.