Memories for Extreme Networking
Presented at MemCon 2014 by Michael Sporer, Director of IC Marketing for MoSys
Abstract:
Designers of networking equipment have had commodity DRAM, on-chip embedded SRAM and everything in between in order to meet extreme performance requirements. The award winning platforms use a combination of memory technologies from high bandwidth and high capacity DRAM for packet buffering as well as both on-chip and off-chip memory solutions for packet header processing. Switch chips that limit themselves to only on-chip memory are suitable for Layer 2 or top-of-rack type switches. In order to go beyond this application space requires memory capacity larger than can be economically deployed on-chip, and once the decision is made to use external memories the on-chip memory can be reduced which in turn enables more silicon area available for value-add functionality. In addition to commodity DRAM for packet buffering, extreme networking equipment traditionally utilized external SRAM, low latency DRAM and content addressable memories (CAM) all of which have connected to the host with a parallel interface. Extreme networking including SDN and NFV, is moving towards higher performance and more highly segmented memory architectures which utilize a serial interface. Further enhancements towards ‘smart memories’ which offload memory intensive operations from the host, including statistics, accounting and search functions enable next generation extreme networking equipment to be able to guarantee quality of service and monetize network bandwidth effectively.