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Implementation of a Multipath Fully Differential OTA in 0.18-μm CMOS Process
FPGA Based True Random Number Generation Using Programmable Delays in Oscillator Rings
AddNet: Deep Neural Networks Using FPGA-Optimized Multipliers
VLSI IEEE Projects 2023 | Check Recent 2023 Research Titles
Variable-Precision Approximate Floating-Point Multiplier for Efficient Deep Learning Computation
VLSI Application, Interface and Mini Projects
A Low-Complexity Multiple Error Correcting Architecture Using Novel Cross Parity Codes Over GF(2m)
Hybrid Protection of Digital FIR Filters
FPGA Implementation of 64 Block Data Encryption Standard Algorithm
FPGA Implementation of a ECG-DAC-SPI Interface for Medical Applications
FPGA Implementation of Image Line Buffer to Split and reconstruct a 3x3 size of image pixel
Probability-Driven Multibit Flip-Flop Integration With Clock Gating
MFCC Feature Extraction using MATLAB
EFFICIENT IMAGE CONVERSION AND RESTORATION SYSTEM WITH HEXADECIMAL ENCODING AND QUALITY EVALUATION
An Innovative Area Efficient Pixel Shuffling Method for Image Encryption Algorithm
An Optimization in Conventional Shift &Add Multiplier for Area-Efficient Implementation on FPGA
Improving Error Correction Codes for Multiple-Cell Upsets in Space Applications
A High Resolution FPGA TDC Converter with 2.5 ps Bin Size and -3.79~6.53 LSB Integral Non linearity
FPGA Implementation of Single Precision Floating Point Multiplier
Design and Implementation of Arithmetic Logic Unit in HDL
FPGA Implementation of 8x8 Truncated Multiplier
New Majority Gate Based Parallel BCD Adder Designs for Quantum-dot Cellular Automata
Speech Encryption Using Chaotic Encryption and Decryption with Hardware FPGA implementation
LOW POWER VLSI IEEE PROJECTS 2025
Design of Approximate Restoring Divider (8/4 Exact and Approximate Architecture)
Image Demosaicking using Super Resolution Techniques
Implementation of High-Precision MFCC Feature Extraction Using FPGA for Speech Recognition
Image Encryption on FPGA Using Chaotic PRNG and LFSR: TFT Display Integration
Design of SEU Tolerant 2D-FFT in SRAM-based FPGA
FPGA Implementation of High Performance Reversible logic based 16x16 Array Multiplier
IEEE Transactions on VLSI 2023 Research Papers
A Deblocking Filter Hardware Architecture for the High Efficiency Video Coding Standard
VLSI IEEE Transactions 2020 | IEEE Transactions on VLSI 2020 | Download VLSI IEEE PROJECTS 2020
Design and Implementation of Efficient Streaming Deblocking and SAO Filter for HEVC Decoder
Design and Evaluation of Inexact Computation based Systolic Array for Convolution
Error Detection and Correction in SRAM Emulated TCAMs
Floating Point Multiplier using Brent Kung Adder
MInSC: A VLSI Architecture for Myocardial Infarction Stages Classifier
FPGA Implementation of Comparative Analysis and Performance Evaluation for Different LFSR Techniques
High Performance FIR and IIR Filters Based on FPGA for 16 Hz Signal Processing
Extraction of Fetal ECG from Abdominal and Thorax ECG Using a Non-Causal Adaptive Filter
A Reversible Processor Architecture and Its Reversible Logic Design
IEEE Transactions on VLSI 2022 Research Papers
Design and Analysis of a Majority Logic Based Imprecise 6-2 Compressor for Approximate Multipliers
A Fully Static Topologically-Compressed 21-Transistor Flip-Flop With 75% Power Saving
FPGA Implementation of 8x8 Truncated Multiplier Using Brent Kung Parallel Prefix Adder
CSPRNG using the PRESENT cipher with Polynomial architecture
Design and Implementation of an 8-bit Approximate Wallace Tree Multiplier for Energy Efficient
Hamming based Single Fault Error Correction Code
Parallel Pipelined Architecture and Algorithm for Matrix Transposition Using Registers
