Probability-Driven Multibit Flip-Flop Integration With Clock Gating
Data-driven clock gated (DDCG) and multibit
flip-flops (MBFFs) are two low-power design techniques that are
usually treated separately. Combining these techniques into a single
grouping algorithm and design flow enables further power savings.
We study MBFF multiplicity and its synergy with FF data-to-clock
toggling probabilities. A probabilistic model is implemented to maximize
the expected energy savings by grouping FFs in increasing order of
their data-to-clock toggling probabilities. We present a front-end design
flow, guided by physical layout considerations for a 65-nm 32-bit MIPS
and a 28-nm industrial network processor. It is shown to achieve the
power savings of 23% and 17%, respectively, compared with designs
with ordinary FFs. About half of the savings was due to integrating the
DDCG into the MBFFs.