A Fully Static Topologically-Compressed 21-Transistor Flip-Flop With 75% Power Saving
An extremely low-powerflip-flop (FF) named topologically-compressed flip-flop (TCFF) is proposed. As compared
with conventional FFs, the FF reduces power dissipation by 75%
at 0% data activity. This power reduction ratio is the highest
among FFs that have been reported so far. The reduction is
achieved by applying topological compression method, merger of
logically equivalent transistors to an unconventional latch structure. The very small number of transistors, only three, connected to clock signal reduces the power drastically, and the smaller total transistor count assures the same cell area as conventional FFs. In addition, fully static full-swing operation makes the cell tolerant of supply voltage and input slew variation. An experimental chip design with 40 nm CMOS technology shows that almost all conventional FFs are replaceable with proposed FF while preserving the same system performance and layout area.