Digitronix Nepal

Simulation with ModelSim: How to load Macro File on Modelsim

Half Unrolling Keccak for reducing area by 50% on VCU1525

Hello World & Peripheral Test with VIVADO, SDK & Ultra96 FPGA- BOOT.BIN Test

Altera Cyclone 10 LP FPGA Board Programming with Quartus Prime Lite Software

Yolo V3 Tiny [Caffe] for Object Detection with DPU DNNDK & Ultra96 FPGA

Zynq Ultrascale+ MPSoC Architecture Overview

SPARTAN3E FPGA UART INTERFACING

Tensorflow Installation on Pynq

Installing Petalinux on Linux [Ubuntu/CentOS/RedHat]

Convolutional Neural Network (CNN) processor design on VHDL/Verilog

Cubehash algorithm of X17 & X16R/S VIVADO Explained

Advance Verilog Design: from Lexical Conventions, Data Flow Modeling to Behavioral Modeling

Vitis Beginner Tutorial- Creating GPIO project

PYNQ VDMA Overlay Design with VIVADO and Python Notebook

Fugue algorithm of X17 & X16R/S Crypto Mining Algorithm Explained

XADC Implementation & Debugging on Zybo FPGA with VIVADO

Logic Gate Design & Simulation in Verilog with Xilinx ISE

How to create Custom IP on VIVADO HLS targeted for Zedboard FPGA

Node MCU Motor Control with IP Address from Smartphone and Web-Browser

Logic Gate (AND gate) Design in VHDL/Verilog in ISE for Spartan 3E by Digitronix Nepal

Basic Logic Gate [AND] Design & Simulation on Verilog

Writing Simulation Testbench on VHDL with VIVADO

Running Tcl Scripts on VIVADO & Zedboard DMA Audio Demo by Digitronix Nepal

Partial Reconfiguration with Xilinx VIVADO tool-An Example Design

Plunify Cloud for FPGA Development-Getting Started by LogicTronix

Adder Design with System Generator (FPGA Design with MATLAB & Simulink)

Custom IP Upload to Zedboard Revision D in QSPI JTAG Mode via Xilinx VIVADO SDK

Installing of Matlab/Simulink and Xilinx ISE/VIVADO for System Generator/HDL Coder

Tutorial on Writing Simulation Testbench on Verilog with VIVADO

Zedboard getting started with VIVADO and SDK Switch Buttons and Led Interfacing with AXI GPIO IP

Install Xilinx VIVADO on Linux [Ubuntu/CentOS]

Mimas V2: Basic Logic Gate Design in VHDL & Implementation with Xilinx ISE tool

PCIe Development with FPGA: Section 5 Lab51 loading ILA data and analyzing the PCIe Packets

FPGA Design with MATLAB/Simulink [System Generator]-Udemy Course

Unboxing ZedBoard FPGA & Features Introduction Session by Digitronix Nepal

PYNQ Development with Python and Xilinx VIVADO- Udemy Course

Video DMA (VDMA) Configuration with Xilinx VIVADO & Zynq FPGA

Creating Custom PYNQ Overlay with VIVADO HLS, IPI and Jupyter

Creating Custom AXI IP on VHDL in VIVADO Design Suit for ZedBoard tutorial from Digitronix Nepal

ATMEGA32 KEYPAD TO LCD INTERFACING

VHDL Programming with Intel Quartus Tool -Course Overview

Advance Verilog Design- Overview, Data Types, Syntax and Semantics

Download & Install Xilinx Vivado & Get 30 day evaluation license

Conditional Statements in Verilog - always block, If-else & case statement

Keccak Bitstream Implementation on ZedBoard FPGA -Proof of Concept Demo

Live Video Streaming Implemented on Zybo-Zynq7000 FPGA with VIVADO Design Suit

Getting Started with ZedBoard with Linux Bootup and Led Blinking by Digitronix Nepal

AES(Advanced Encryption Standard) Encryption/Decryption Algorithm Overview with VHDL/Verilog

Webinar Series on FPGA: Computer Vision & Machine Learning with FPGA, Feb 17 2019

Interfacing Zedboard FMC-HDMI & Zybo FPGA for Video Processing