Verilog Coding - Verification, Xilinx ISE, Register, Add, Multiply, Logic Design Lec 16/26
Topics Covered:
0:00 Verilog Coding Review
02:56 Register, Posedge Clk,
08:46 Blocking and Non-Blocking Assignment
21:52 Adder, Subtractor, Multiplier
27:14 Declarations
34:52 Coding steps
36:31 Verilog Coding Example: Counter
46:30 Verilog Simulation/Testing/Verification
52:30 Testbench,
56:44 Module Instantiation
1:02:15 Clock Generation, Initial block, Forever loop
1:06:12 Main Simulation, Delays using # and @(posedge clk)
1:14:22 Using Xilinx ISE Project Navigator
1:15:00 Creating a Project
1:17:20 Adding Verilog Files
1:18:50 Adding Test Bench
1:20:41 Design Simulation
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Slides available at: https://tinyurl.com/dld-slides
Slides used in this lecture are part of "FPGA based Design" Training program at Renzym
http://www.renzym.com/trainings.html
This course was taught at Abasyn University Islamabad, Fall 2016
http://www.abasynisb.edu.pk/