127 тысяч подписчиков
382 видео
Verilog in 2 hours [English]
Processor design for dummies [English]
Machine Learning in 5 hrs [Urdu/Hindi]
The AXI Protocol, AXI MM and AXI Streaming Interfaces [English]
Digtal Logic Design crash course in 4 hrs [Urdu/Hindi]
Computer Architecture Crash Course [Urdu/Hind]
Python/Numpy/Jupyter in 2 hrs [Urdu/Hindi]
Making peace with complex numbers [English]
FPGA Block RAM (BRAM) Verilog code
C++ crash course in 3 hrs [Urdu/Hindi]
STL (Standard Templates Library) C++ [Urdu/Hindi]
Using Git with Vivado and Xilinx SDK [Urdu/Hindi]
Verilog Coding - Verification, Xilinx ISE, Register, Add, Multiply, Logic Design Lec 16/26
VGA Interface, Image Display on FPGA's VGA Interface, Logic Design Lec 23/26
Logic Design Review, FPGA based design using Verilog 1/5
Visual Studio Community Edition Installation (2019) for C++ Programming
Verilog Coding - State Machines coding, Random Verification, Logic Design Lec 24/26
Fall 2020 - VGA on FPGA displaying image stored in BRAM [Urdu/Hindi]
Procedures (Functions) in Assembly, Microprocessor based Systems Lec 27/31
Synthesis using Xilinx Vivado, FPGA based design using Verilog 4/5
Verilog simulation using Vivado, FPGA based design using Verilog 3b/5
AXI based Design using Xilinx Vivado, Digital System Design Lec 19/21
