Verilog in 2 hours [English]
#verilog #asic #fpga
This tutorial provides an overview of the Verilog HDL (hardware description language) and its use in programmable logic design. We cover logic design process and then both synthesis constructs of Verilog as well as simulation constructs. We also discuss writing Verilog code for state machines. You will gain a basic understanding of Verilog enabling you to begin creating your designs. You can jump to relevant sections by clicking at time tags in the CONTENT below.
Slides and Solutions:
https://tinyurl.com/verilog-slides
Icarus Verilog installation:
• iVerilog Install
Try Verilog without installation on edaboard.com
• EDA Playground Introduction -- Simulate Ve...
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CONTENT
(0:00) Course Overview
(1:34) PART I: REVIEW OF LOGIC DESIGN
(2:35) Gates
(4:24) Registers
(9:06) Multiplexer/Demultiplexer (Mux/Demux)
(10:16) Design Example: Register File
(13:56) Arithmetic components
(15:31) Design Example: Decrementer
(21:50) Design Example: Four Deep FIFO
(30:35) PART II: VERILOG FOR SYNTHESIS
(31:06) Verilog Modules
(37:20) Verilog code for Gates
(38:38) Verilog code for Multiplexer/Demultiplexer
(45:34) Verilog code for Registers
(48:11) Verilog code for Adder, Subtractor and Multiplier
(50:09) Declarations in Verilog, reg vs wire
(52:42) Verilog coding Example
(59:32) Arrays
(1:01:54) PART III: VERILOG FOR SIMULATION
(1:02:37) Verilog code for Testbench
(1:06:44) Generating clock in Verilog simulation (forever loop)
(1:08:31) Generating test signals (repeat loops, $display, $stop)
(1:16:06) Simulations Tools overview
(1:18:19) Verilog simulation using Icarus Verilog (iverilog)
(1:28:03) Verilog simulation using Xilinx Vivado
(1:37:02) PART IV: VERILOG SYNTHESIS USING XILINX VIVADO
(1:42:42) Design Example
(1:46:10) Vivado Project Demo
(1:49:49) Adding Constraint File
(1:54:25) Synthesizing design
(1:57:58) Programming FPGA and Demo
(2:00:31) Adding Board files
(2:01:44) PART V: STATE MACHINES USING VERILOG
(2:10:42) Verilog code for state machines
(2:17:22) One-Hot encoding