ASIC Design Flow.avi
ASIC design flow
Starts with a Verilog design File down to place and route the chip.
FPGA Advantages debugs and translates the Verilog file to Verilog95.
LeonardoSpectrum reads the Verilog95 file and synthesizes it using the tsmc0.18u technology library.
TannerEDA S-Edit imports the generated Verilog netlist using the same technology and exports a Tanner Place and Route (tpr) file
TannerEDA L-Edit reads the tpr file and does a place and route using Standard Place and Route (SPR) i.e. channel routing
The PADs does not work for this library.
another schematic design with PADs using another library in the following two links: • Using TannerEDA S-Edit.avi
and
• TannerEDA L-Edit Standard Place and Route ...