Design of I2C Master Core with AHB Protocol for High-Performance Interface
This project explains a block that communicates between the processor and any IC. Generally, this needs two different modules in between. But here, both are integrated as one to avoid external peripheral usage. The incorporation of the Inter-Integrated Circuit (IIC) master module in the Advanced High-Performance Bus (AHB) protocol in order to merge the merits of both IIC and AHB in terms of performance and speed. Considering these aspects, the functional coverage for the base master module (AHB) is obtained to be 100%. In terms of performance, with 2 phase cycle methodology, the data is obtained without any clash and traffic.
Project Type – Front End
Software Used –Xilinx ISE