The method of low power, high performance and area efficient address decoder design for SRAM

Design of I2C Master Core with AHB Protocol for High-Performance Interface

VLSI Implementation of Error Detection and Correction Codes for Space Engineering

Design and of Encryption/ Decryption Architectures for BFV Homomorphic Encryption Scheme

Design and Simulation of CRC Encoder and Decoder using Verilog

The method of low power, high performance and area efficient address decoder design for SRAM

A POWER EFFICIENT AND DELAY OF CMOS PHASE DETECTOR AND PHASE FREQUENCY DETECTOR USING NANO DIMENSION

3 days Online training Program on MSP430 & MATLAB ( DAY - 1)

Design of a Two-Bit Magnitude Comparator Based on Pass Transistor, Transmission Gate, Static CMOS

Lossless EEG Compression Algorithm Based on Semi- Supervised Learning for VLSI Implementation

Detection of Power Grid Synchronization Failure by Using GSM Technology

Design of digital circuit implementation using GDI and CMOS Technology

Design and Implementation of Vehicle Data Transmission Protocol Based on PRESENT Algorithm