Unlocking RISC V’s potential on Intelligence Application Processing
【2024 ANDES RISC-V CON Silicon Valley】
DEEP DIVE INTO AUTOMOTIVE / AI / APPLICATION PROCESSORS AND SECURITY TRENDS
📍About The Event
Recently, RISC-V, with its open, streamlined, and scalable configuration, has become the mainstream solution adopted by leading market players, paving the way for widespread technological innovation. In the RISC-V application field, there has been rapid development in forward-looking areas such as automotive electronics and AI. The development application processors has attracted a lot of attention, and the need for product information security has also increased.
As a Premier member and a leading brand in 32/64-bit embedded CPU cores, Andes, a member of RISC-V International, will host an annual seminar on June 11 at the DoubleTree by Hilton San Jose. The theme of the seminar is "ANDES RISC-V CON: Deep Dive into Automotive/AI/Application Processors and Security Trends." The event aims to introduce the market dynamics and development trends of RISC-V, discuss Andes' comprehensive product portfolio recently launched, and assist industries in fully utilizing the high-performance/low-power characteristics of the RISC-V architecture to enhance product competitiveness and move towards a future full of opportunities.
The seminar will feature presentations and on-site demonstrations by numerous RISC-V ecosystem partners, providing insights into the latest international trends and technological developments in RISC-V. Let us join hands to celebrate this event and explore the potential of RISC-V together with industry experts, paving the way for a diverse application vision!
📍Speaker : Dr. Charlie Su, President & CTO, Andes
Dr. Charlie Su is the first employee of Andes. He is in charge of product development and technical marketing. He spent over 12 years in the Silicon Valley with various technical and management positions at Sun Microsystems, Afara Websystems, C-Cube Microsystems, SGI/MIPS, and Intergraph.
He made key contributions to several successful processors such as the Sun multi-core multi-threading Ultrasparc T1 and T2 processors, the C-Cube high-performance E-series MPEG media processors, the MIPS out-of-order R10K processor, and the Intergraph Clipper VLIW processor. Prior to starting Andes, he led the CPU and DSP development in Faraday Technology as Chief Architect.
Charlie obtained his Ph.D. in Computer Science from the University of Illinois at Urbana-Champaign, M.S. in Computer Science from National Tsing-Hua University, and B.S. in Electrical Engineering from National Taiwan University.