Verilog Coding - State Machines coding, Random Verification, Logic Design Lec 24/26
Topics Covered:
Verilog Coding of State Machines 0:00
Mealy and Moore Machines,
One hot encoding
Methodical Verification 40:06
Directed Verification, Rigorous Verification,
Random Verification, Hybrid Approach
Verilog code for FIFO Random Verification
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Slides available at: https://tinyurl.com/dld-slides
Slides used in this lecture are part of "FPGA based Design" Training program at Renzym
http://www.renzym.com/trainings.html
This course was taught at Abasyn University Islamabad, Fall 2016
http://www.abasynisb.edu.pk/