ECG Decompression | A VLSI-Based Hybrid ECG Compression Scheme

IEEE Transactions on VLSI 2024 | VLSI Phd Research Guidance

Efficient Approximate Floating-Point Multiplier with Runtime Reconfigurable Frequency and Precision

FPGA Implementation of 8x8 Truncated Multiplier Using Brent Kung Parallel Prefix Adder

Efficient CRC-BCH Unified Encoder for Global Positioning System

FPGA Implementation of Comparative Analysis and Performance Evaluation for Different LFSR Techniques

Design and Implementation of 32-bit CSPRNG using the PRESENT cipher with Dual Polynomial PRNG

Ultra Lightweight Cryptography: Exploring the Application and Optimization of the PRESENT Cipher

Efficient Pseudo Random Number Generator (PRNG) Design on FPGA

Optimized Dual Accumulator based RISC Architecture with Advanced Memory and Peripheral Operations

Hardware-Efficient Logarithmic Floating-Point Multipliers for Error-Tolerant Applications

A High Speed CRC-32 Implementation on FPGA

High Performance FIR and IIR Filters Based on FPGA for 16 Hz Signal Processing

Soft-Error-Aware SRAM with Multinode Upset Tolerance for Aerospace Applications

EFFICIENT IMAGE CONVERSION AND RESTORATION SYSTEM WITH HEXADECIMAL ENCODING AND QUALITY EVALUATION

Design and Evaluation of Inexact Computation based Systolic Array for Convolution

Extraction of Fetal ECG from Abdominal and Thorax ECG Using a Non-Causal Adaptive Filter

Parallel Pipelined Architecture and Algorithm for Matrix Transposition Using Registers

ECG Decompression | A VLSI-Based Hybrid ECG Compression Scheme

A Reversible Processor Architecture and Its Reversible Logic Design

Design and Analysis of a Majority Logic Based Imprecise 6-2 Compressor for Approximate Multipliers

MInSC: A VLSI Architecture for Myocardial Infarction Stages Classifier

Fast and Hardware-Efficient Variable Step Size Adaptive Beamformer

Design of High Speed 8-bit Vedic Multiplier using Brent Kung Parallel Prefix Adder

Design and Implementation of an 8-bit Approximate Wallace Tree Multiplier for Energy Efficient