Dataflow Modeling - Verilog Fundamentals
This video explains Dataflow Modeling in Verilog, which is a fundamental tool used in Verilog programming. We'll also see some great examples of dataflow modeling in action.
If you're new to Verilog programming, or want to improve your skills, then this video is for you! By the end of this video, you'll have a basic understanding of the dataflow model, and be able to use it to design simple circuits in Verilog.
LINKS
https://github.com/kirkster96/verilog...
CHAPTERS
00:00 Introduction
00:50 Continuous Assignment
02:50 Arithmetic Operators
03:25 Demo 11: 32-bit Full Adder
05:20 Relational and Equality Operators
06:04 Demo 12: Case Equality
09:57 Bitwise and Logical Operators
10:20 Demo 13: Bitwise vs Logical
17:46 Reduction Operators
18:10 Demo 14: Parity Bit
22:04 Shift Operators
22:32 Demo 15: Bit shifting
32:21 Concatenation, Replication, and Conditional Operators
32:54 Demo 16: 2-to-1 mux
35:28 Module Summary
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