Next-Generation Vector Processor Design III
#RISCV #vector #processor #AndesTech
2021 Andes RISC-V CON Webinar
Date: August 31, 2021
Topic: Next-Generation Vector Processor Design III
Speaker: Thang Tran, Principal Architect, Andes Technology
The event is the third of a 4-part lecture series on next-generation vector processor design. It showcases a 5-stage pipeline and an 8-stage in-order superscalar vector processor based on Andes’ latest AndeStar™ V5 Architecture. Both have design wins at major TSMC foundry customers.
Dr. Thang Tran, Principal Architect and veteran of high-performance computing (HPC) at Andes Technology is the series' presenter. Dr. Tran is an industry expert in HPC development. He architected and designed the Andes RISC-V out-of-order (OOO) Vector Processor (VLEN/SIMD=512b) in 9 months using a revolutionary algorithm that does not resemble any previous known OOO superscalar design that has no temporary registers (not renaming, not re-order buffer).
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