INTRODUCTION TO LATCHES and FLIP-FLOPS

IMPORTANT QUESTIONS ON PARITY GENERATOR

PARITY GENERATOR IT'S TRUTH TABLE AND CIRCUIT DESIGNING

JK FLIP-FLOP USING NAND GATE ; TRUTH TABLE, CHARACTERISTIC TABLE AND EXCITATION TABLE

D FLIP-FLOP USING NAND GATE, TRUTH TABLE, CHARACTERISTIC TABLE AND EXCITATION TABLE

SR FLIP-FLOP USING NAND GATE, TRUTH TABLE ,CHARACTERISTIC TABLE AND EXCITATION TABLE

SR LATCH using NAND GATE

INTRODUCTION TO LATCHES and FLIP-FLOPS

SEQUENTIAL CIRCUITS, CLOCK PULSE and TRIGGERING

ENCODERS ( OCTAL TO BINARY ENCODER & DECIMAL TO BCD ENCODER)

FULL ADDER DESIGNING USING DECODER AND DESIGNING EXPANDED DECODERS

DECODER CONCEPT AND CIRCUIT DESIGNING

DEMULTIPLEXER WORKING and CIRCUIT DESIGNING

DESIGNING OF FULL ADDER USING 4:1 MULTIPLEXER

IMPLEMENTATION OF BOOLEAN FUNCTIONS USING MULTIPLEXER

8:1 MUX and 16:1 MUX using 4:1 MUX

MULTIPLEXER TREE (4:1 and 8:1 MUX using 2:1 MUX)

DESIGNING OF LOGIC GATES USING 2 : 1 MULTIPLEXER

MULTIPLEXER

FULL SUBTRACTOR

HALF SUBTRACTOR

FULL ADDER

COMBINATIONAL and SEQUENTIAL CIRCUITS (HALF ADDER)

PRIME, ESSENTIAL, SELECTIVE and REDUNDANT IMPLICANTS

Don't care condition in SOP and POS K-Map