SR Latch with NAND gates and D Latch explained in 10 Minutes
#nand #srlatch #digitallogicdesign
When using static gates as building blocks, the most fundamental latch is the simple SR latch, where S and R stand for set and reset. It can be constructed from a pair of cross-coupled NOR or NAND logic gates. The stored bit is present on the output marked Q.
The circuit explained in the video is a basic NAND latch. The inputs are generally designated S and R for Set and Reset respectively. Because the NAND inputs must normally be logic 1 to avoid affecting the latching action, the inputs are considered to be inverted in this circuit (or active low).
The circuit uses feedback to "remember" and retain its logical state even after the controlling input signals have changed. When the S and R inputs are both high, feedback maintains the Q outputs to the previous state.
The R = S = 0 combination is called a restricted combination or a forbidden state because, as both NAND gates then output 1s, it breaks the logical equation Q = not Q. The combination is also inappropriate in circuits where both inputs may go high simultaneously (i.e. a transition from restricted to keep). The output would lock at either 1 or 0 depending on the propagation time relations between the gates (a race condition). In certain implementations, it could also lead to longer ringings (damped oscillations) before the output settles, and thereby result in undetermined values.