Positive Edge triggered D flip flop with clock edges explained
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As a number of issues and defects have been witnessed as a result of application of level clocking, therefore edge triggering mechanism has generally been preferred over level clocking. According to which, output condition of a flip-flop changes only when clock pulse is on its rising or falling edge. In other words, when a circuit is edge-triggered, its output changes only on rising or falling edge. It further means that when square shaped clock pulse is on positive going edge (i.e. in descending form) output changes. A D-type flip-flop which changes its output on positive going edge, is called positive edge-triggered flip-flop. And a D type of flip-flop, which changes its output on negative going edge, is called negative edge-triggered D flip-flop.
In short, when circuit is activated through transition portion of a clock, it is called edge-triggering. However, when the circuit is activated via voltage level, it is known as level triggering. In order to fully comprehend edge-triggering, a square wave has been illustrated in figure 5.14 (a), which represents a full cycle of clock pulse. This whole cycle can be divided into following different portions.