Cadence Virtuoso: Master the Common Drain Amplifier Layout | Source Follower | VLSI Lab #10
🚀 *Common Drain Amplifier Layout Design*
Welcome to VLSI Lab #10!
Today, we are stepping into analog design by building the Common Drain Amplifier Layout (also known as the Source Follower).
*While the schematic might look simple*, the *physical layout requires precision to manage parasitics and ensure your simulation matches reality*.
*In this tutorial, I’ll show you the step-by-step workflow in Cadence Virtuoso (GPDK 180nm)—from the initial routing to the final Assura - DRC, LVS & QRC extraction*.
📌 What You’ll Learn Today:
💥 Analog Routing: Handling the bias and load connections without creating massive parasitic resistance.
💥 The "Integrated Body" Trick: Why setting the body to "Integrated" is a lifesaver for amplifiers.
💥 Post-Layout Simulation: Using QRC Extraction to see the real-world performance of your amplifier.
📔 *Lab Survival Kit!*
😳 Stuck on DRC/LVS errors?
😏 Don't worry, Didi Hai Na! I am preparing these resources to help you finish your labs in record time.
*Stay Tuned*
💥 *The CMOS Inverter Design & Verification Manual*: A 5-chapter deep dive into the full Cadence workflow . It covers everything from Environment Setup to Parasitic Extraction.
💥 *The Ultimate Shortcut Cheat Sheet*: Every key you need for Schematic, Layout, and Waveforms on one page!
🚀 *Join the Tribe!*
💥 Become a channel member for exclusive perks, including:
💥 Member-Only Doubt Solving: Post your error screenshots in our community tab!
⏰ *Timestamps* :
00:06 – Let's Begin!
00:38 – Launch Layout XL
01:15 – Connectivity: Generate All from Sources
01:41 – Remember: Both MOSFETs are nMOS!!!
02:04 – Why is the width of these MOSFETs important???
02:35 – How do we connect the Body terminals here???
02:46 – What are the Pins we have with us?
04:26 – Connectivity: Show/Hide All Incomplete Nets
04:49 – Let's get the Body Terminals!
06:09 – Complications Ahead!!!
07:01 – Error Avoidance: Rotate the MOSFET!
08:43 – Who is the Source Terminal???
10:51 – Let's start the connections!
17:28 – And the Layout is Done!!!
18:08 – Time for ASSURA
18:15 – Run DRC
18:43 – DRC Error Debugging
19:31 – Run LVS
20:23 – Run QRC
21:09 – av_extracted view
21:25 – Shift + F & view the Parasitics!
22:19 – Next Lab: Layout of Common Source Amplifier
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👉🏻 *Prerequisites* :
Lab #5 :
• Cadence Virtuoso Tutorial : Designing a Co...
Lab #6 :
• Cadence Virtuoso: Common Drain Amplifier S...
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