Cadence Virtuoso: CMOS Inverter Layout Design [Step-by-Step] | VLSI Lab #8
📌 *Cadence Virtuoso: CMOS Inverter Layout Design [Step-by-Step] | VLSI Lab #8*
Welcome to Lab #8! In this video, we we walk through the complete CMOS Inverter layout design process using Cadence Virtuoso.
Whether you're a student, a fresher, or a professional brushing up on analog layout skills, this step-by-step guide will help you create a clean, DRC-clean layout from scratch.
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🔧 *In this video, you’ll learn:*
How to start a new layout in Cadence Virtuoso
NMOS and PMOS transistor placement and matching
Layer-by-layer drawing (Active, Poly, Metal1, Contacts)
Design rule considerations and best practices
⏰ *Timestamps*
0:15 - What we have achieved so far
0:55 - Lets Design the Layout of CMOS Inverter
1:28 - Step 1: Which Schematic to Choose?
2:32 - Step 2: Launch Layout XL!
3:55 - Step 3: We have the Layout Window!
4:22 - Step 4: Generate - All From Source
4:58 - Thats how a PR (Placement & Routing) Boundary looks like
6:30 - Step 5: Layout View of pMOS & nMOS
7:16 - Internal Structure of MOSFETs - Where are the Gate, Source & Drain Terminals?
8:14 - Why so Colourful?
9:33 - Step 6: Nets - Show/Hide All Incomplete Nets
11:24 - Step 7: What if I forget which Pin or Component I am dealing with???
12:24 - What if I don't check with the Schematic?
13:26 - Step 8: Layout should always match the Schematic!
14:02 - Step 9: Drag & Drop those Components!
15:52 - Step 10: Let's Connect all the Nets!
17:28 - Step 11: How to Avoid ERRORS!
18:32 - Step 12: Always use Arrow keys in Layout!
19:20 - Gate Terminals are Connected!!!
19:30 - Step 13: How to Connect Metal to Poly!
21:45 - Input Connection is Complete!!!
22:00 - Step 14: Which one is Source & Drain?? Where's the Body Terminal??
22:40 - Step 15: Let's find the Body Terminal!!! (Integrated/Detached)
25:35 - Step 16: That's where our Source & Drain Terminals are!!!
26:07 - Step 17: How to Connect Metal to Metal???
27:25 - Output Connection is Complete!!!
27:36 - Step 18: Connecting Vdd & GND
29:46 - That's our CMOS Inverter Layout!!!
30:15 - Next Lab - New Tool - ASURA!!!
🎓 *This tutorial is part of the VLSI Lab Series – perfect for:*
VLSI / Analog IC Design students
Physical Design enthusiasts
Engineers preparing for interviews
Anyone learning Cadence Virtuoso tools
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👉 *Next in VLSI Lab Series:*
DRC, LVS (Layout vs. Schematic) verification.
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