(EN) AndeSysC™ - A Flexible RISC-V Processor Model for SoC Virtual Prototyping
2021 Andes RISC-V Webinar
Date: March 25, 2021
Topic: AndeSysC™ - A Flexible RISC-V Processor Model for SoC Virtual Prototyping
Speaker: YiChiang Chang, Technical Marketing Manager, Andes Technology
Slides for this presentation are available here:
http://www.andestech.com/wp-content/u...
AndeSysC™ is Andes virtual platform solution based on SystemC to enrich the RISC-V ecosystem. It provides extendable, flexible and near-cycle accurate models of AndesCore™ V5 RISC-V processor IP’s and components for hardware designers to construct SoC prototypes and evaluate and verify their architecture, functionalities and performance before committing to the actual hardware implementation. With virtual models of Andes processors, AndeSight™ IDE and AndeSoft™ software stack, software engineers can jump-start their development on profiling, optimizing, debugging, and testing in parallel to hardware development to accelerate the development cycle of the complex design. In this talk, we will provide an overall picture of Andes and RISC-V momentum. Then we will introduce the concept of the virtual prototyping and AndeSysC™ with a virtual SoC example that fully utilizes the features from AndeSight™ to expedite the development cycle.
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