A reusable verification, emulation and validation flow for ASIC design (Tomasz Hemperek)
In the conventional ASIC design life cycle, distinct teams are assigned to ASIC design/verification, firmware design/verification, and software development, leading to separate timelines and potential communication gaps. Consequently, issues detected during firmware or software phases can be challenging and expensive to correct.
The presented reusable approach allows all teams to work concurrently, ensuring improved coordination and faster development cycles. Moreover, it facilitates the majority of the work to be completed even before the final silicon is ready, resulting in a more robust and efficient ASIC design process.
We present a practical implementation of an reusable design flow that uses open-source tools.