FOSSi Foundation

spinal.lib.bus.tilelink : An Tilelink interconnect generator based on fiber (Charles Papon)

Complex system simulation and HW/SW co-design with Renode open source simulation framework

DPI protected Verilog instead of encryption - Todd Strader - ORConf 2019

OSVVM, VHDL's #1 FPGA Verification Library

Architecture 2.0: Toward Open Source Foundation Models and Datasets for Hardware Design

"ChipWhisperer: Past & Future of a FPGA-based Research Tool" - Jean-Pierre Thibault (Latch_2024)

"Clean up your EDA flows with tclint" - Noah Moroze (Latch_2024)

"HDLAgent, Enhancing Hardware Language in the age of LLMs" - Jose Renau (Latch_2024)

"Beyond EDA lies Edalize" - Olof Kindgren (Latch_2024)

Status of Xilinx Artix 7 support in Symbiflow - Tim 'mithro' Ansell - ORConf 2019

OpenRAM: An Open Source Memory Compiler

"CACE Study: Open source analog and mixed-signal design flow" - Tim Edwards (Latch_2024)

Higher-Order Hardware Design with Chisel 3

SystemVerilog-Style Constraints and Functional Coverage in Python

"CoreScore like never before" - Olof Kindgren (Latch_2024)

Bender: A dependency maganement tool for hardware design projects

"Open-source Hardware for Real-Time Applications" - Francisco Wilken (Latch-Up 2023)

Towards xBGAS on CHERI: Examining the Benefits of a Secure Distributed Architecture

"Where Community Powers Innovation" - Mohamed Kassem (Latch_2024)

"ABC: The Way It Should Have Been Designed" - Alan Mishchenko (Latch_2024)

[FOSSi Dial-Up] Jonathan Balkind - Growing OpenPiton

spinal.lib.bus.tilelink : An Tilelink interconnect generator based on fiber (Charles Papon)

"Tim's Silicon Presentations" - Tim Ansell (Latch_2024)

"Teaching Modern EDA using a Tapeout-Centric University Course" - Anish Singhani (Latch_2024)

"Riding The Wave: Building Wave Pipelines in FPGAs" - Rice Shelley (Latch_2024)

MRPHS: Enabling Transaction-level Deductive Formal Verification Through PDVL

"Chisel 6 and beyond" - Jack Koenig (Latch_2024)

A History of TL-Verilog Google Summer of Code Projects under FOSSi Foundation

OSHHISS Open Source for Hybrid Hetrogenous Integrated Semiconductor Systems

A fully-tested 32-bit RISC-V microcontroller in 130nm and board development - ORCONF 2016

Space - Opportunities, Challenges for Open Source Community - Chinh Le (Latch-Up 2023)

FireSim: A Scalable Platform for FPGA-Accelerated Simulation [..] - Sagar Karandikar (Latch-Up 2023)

pyfda: Python Filter Design and Analysis (Christian Muenker)

Roadmap for Open Source EDA in Europe (Stefan Wallentowitz)

RISC-V in Debian

A reusable verification, emulation and validation flow for ASIC design (Tomasz Hemperek)

"Tiny Tapeout: custom silicon open to all" - Pat Deegan (Latch_2024)

Accelerating Chisel Development - Jack Koenig (Latch-Up 2023)

Bootstrapping a real working design flow

The CERN OHL v2 and copyleft licences for HDL - ORConf 2017

Sonata: A development platform to enable exploring the use of CHERI for embedded applications

My open source analog microelectronics journey (Matt Venn)

"UMI: Universal Memory Interface" - Andreas Olofsson (Latch_2024)

Open-Source FPGA tools, how and why?

"Artifact Evaluation for the Field Programmable Gate Array Community" - Miriam Leeser (Latch_2024)

[FOSSi Dial-Up] Tim Ansell - Skywater PDK: Fully open source manufacturable PDK for a 130nm process

Hammer: A Modular and Reusable Physical Design Flow Tool - Nayiri Krzysztofowicz (Latch-Up 2023)

Open Source SCR1 core - Ekaterina Berezina - ORConf 2019

Practical aspects of using the Open Source SCR1 core - Ekaterina Berezina - ORConf 2018

"From an Open-Source ISA to Open-Source HW to Open-Source Silicon" - Luca Bertaccini (Latch_2024)

"Accelerating Hardware Design with Custom GPTs" - Prakash Shvetank (Latch_2024)