Practical aspects of using the Open Source SCR1 core - Ekaterina Berezina - ORConf 2018
SCR1 is an open-source MCU-class RISC-V core for deeply embedded applications and accelerator control, developed and maintained by Syntacore. It can be configured for both RV32I and RV32E base instruction sets and also supports optional M and C extensions. SCR1 has been released under permissive Solderpad Hardware License at the 5th RISC-V Workshop and, since then found considerable traction both in the industry and academia. In this session, we provide deep-dive into core features and usage scenarios accumulating about a year of experience supporting it. Our presentation is targeted at advanced users and provides in-depth information about SCR1 usage and bring-up, its configurable features and implementation cost and performance impact.
Presenter: Ekaterina Berezina
Ekaterina Berezina is HW Engineer at Syntacore, where she contributes to the SCRx core family development in the RTL designer role. Ekaterina is one of the SCR1 core developers and maintainers. She received her Master’s degree in Computer Science at ITMO University, Saint-Petersburg.
Talk recorded at ORConf 2018, the Open Source Digital Design conference, held in Gdansk, Poland and organized by the FOSSi Foundation.