OSVVM, VHDL's #1 FPGA Verification Library
Jim Lewis
Open Source VHDL Verification Methodology (OSVVM) is an ASIC
level VHDL verification methodology that is simple enough to use
even on small FPGA projects. OSVVM offers the same capabilities
as other verification languages such as SystemVerilog and UVM.
This presentation provides an overview of OSVVM's capabilities, including:
Transaction-Based Modeling
Constrained Random test generation
Functional Coverage with hooks for UCIS coverage database integration
Intelligent Coverage Random test generation
Utilities for testbench process synchronization
Transcript files
Error logging and reporting – Alerts and Affirmations
Message filtering – Logs
Scoreboards and FIFOs (data structures for verification)
Memory models
The FOSSi Foundation is proud to announce Latch-Up, a conference dedicated to free and open source silicon to be held over the weekend of May 4th and 5th in Portland, Oregon, USA.
Latch-Up: a weekend of presentations and networking for the open source digital design community, much like its European sister conference ORConf.
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OpenHardware
Sun May 5 10:00:00 2019 at Revolution Hall