20 тысяч подписчиков
99 видео
SDC file | Synopsys Design Constraints file | various files in VLSI Design | session-4
Pcell (parametrized cell) implementation on layout in Cadence Virtuoso | pcell with Example | part-4
Logic Synthesis of RTL | Synopsys Design Compiler | Synopsys DC | dc_shell | DC Tutorial
Crosstalk issue in VLSI | Signal Integrity | crosstalk glitch | crosstalk Noise | part-1
Library files format conversion | .lib to .db | .db to .lib | Library Compiler of Synopsys
Value Change Dump | .vcd file | Switching Activities Interchange Format | .saif file
Clock Latency in VLSI | Source Latency | Network Latency | Insertion Delay
Equations writing in LaTex | Equation copying from another place to LaTex | MathPix snaping tool
URL Citation in LaTex | How to cite URL /web link in LaTex
VLSI ASIC Design Flow | ASIC Flow | Physical Design Flow | Back end design flow | RTL 2 GDS flow
Standard Cell | Standard Cell Layout | Standard Cell Library | Tracks of Standard cells
FPGA Design Flow | FPGA Flow
Spare Cell in ASIC Design | Use of Spare Cells | How to add spare cells in design
Antenna Effect Prevention Techniques in VLSI Design
Latch-up prevention in CMOS | Various techniques for latch-up prevention | Issues in Physical design
Virtual Box + CentOS Installation on window 10 | Download CentOS | Install Linux
Live Demo of FPGA board programming | Verilog coding in Xilinx ISE| Spartan-6 FPGA |
Derivation for Setup and Hold equations | between +ve and -ve flip flops | Half cycle path | Part-2
Multi cycle path in VLSI | Multi cycle path Constraint | Multi cycle path example
Integrated Clock Gating Cell | ICG Cell in VLSI | Clock Gating Cell | Low Power Techniques in VLSI
SPEF file in VLSI | Standard Parasitic Exchange Format file | .spef file in Physical Design
Sentaurus TCAD tutorial | Part 2 | MOS Transistor simulation
Linux installation in VirtualBox | CentOS 7 installation in Oracle VirtualBox
Calibre EDA tool | Installation and integration with cadence virtuoso
Auto License UP on reboot | EDA tools License Administration | Cadence | Synopsys | Mentor license
LIB file | DB file | Verilog file | Description of various files used in VLSI Design | session-1
End Cap or Boundary Cell | Use of endCap Cells | Placement of endCap Cell | Layout of endCap Cell
OCV, AOCV and POCV : a comparative study | difference among OCV, AOCV and POCV | Process Variations
Virtual box installation using command line in CentOS | VirtualBox installation in Linux
Latch and Flip Flops in ASIC Design
Place and Route in Cadence Innovus | full PnR flow | Cadence Innovus demo I Innovus Tutorial
Crosstalk issue and prevention techniques | Crosstalk delay | Shielding of net | part-2
working with Xilinx ISE | FPGA Programming using Verilog | Spartan-6 | Seven Segment Display Driver
Semiconductor Device Simulation using TCAD | Sentaurus TCAD | Part-1 | Introductions
50 Most Useful Linux Commands | Part-2 | Linux tutorial
Setup and Hold Timing Equations - S-01| Easy Explanation with Examples | Same types of FF
Reason for Setup and hold time in flip flop | Setup and hold time | clock to q delay | FF using Mux
Logic Synthesis flow | RTL Synthesis flow | RTL2GDS | Design Compiler (DC) tutorial
Tie Cell in ASIC Design | Use of Tie cell | Schematic and Layout of Tie cells | How Tie cells work
Data and Clock Path | Launch and Capture Flops | Cell delay | Net Delay
Setup and Hold time inside Latch
Synopsys EDA tools Installation | Synopsys tool installation demo
RTL to GDSII flow | Basic terminology used in the ASIC flow | Various EDA tools
Standard Cell Library | Various Cells in Standard Cell Library | Various Files in Standard Cell Lib
User Management in Linux | Linux System Administration | Part-1
bashrc or cshrc setup for EDA tools | Cadence cshrc | synopsysys bashrc | all tool's bashrc setups
DECAP Cell | Use of DeCap Cells | Placement of DeCap Cell | Layout of DeCap Cell
IR Drop issue in VLSI | What is IR drop in ASIC | Why IR Drop | Effects of IR Drop
Clock Skew in VLSI | Positive Skew | Negative Skew | Global Skew | Local Skew
Layout design of nMOS transistor from scratch in Cadence Virtuoso | Part-1
