Derivation for Setup and Hold equations | between +ve and -ve flip flops | Half cycle path | Part-2

Опубликовано: 25 Октябрь 2024
на канале: Team VLSI
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Setup and Hold Time equation between positive and negative edge triggered flip flops have been derived. Such a path is called a Half cycle path. Setup and hold time equations have been derived step by step with easy explanation. The flow of this session is as follow:
0:00 Introduction
1:20 Derivation for setup equation from a negative edge triggered FF to a Positive edge-triggered FF
9:00 Summary of setup time calculation
11:32 Derivation for Hold Equation from a negative edge triggered FF to a Positive edge-triggered FF
18:20 Summary of hold time calculation
20:25 Thanks
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