Setup and Hold Timing Equations - S-01| Easy Explanation with Examples | Same types of FF
Timing is everything for an ASIC design and Setup and Hold timing analysis is an important aspect in timing signoff of ASIC.
The Setup and Hold Timing equations have been derived in this tutorial in a very easy way. Timing analysis has been explained with some relevant example and way of fixing the setup and hold has also been explained.
Timeline of Video:
0:00 Introduction
0:45 Possible scenarios for Analysis
3:33 Derivation for Setup time equation
12:11 Setup Slack
14:09 Example of Setup timing
16:55 Way to fix Setup violation
17:50 Vt Swap
20:10 Early and Late clocking
23:58 Derivation for Hold timing equations
26:28 Why Hold analysis in the same edge of the clock
30:29 Hold Slack
32:42 Question-1
33:03 Example of Hold timing analysis
35:00 Hod violation fixing
37:00 Setup and Hold timing equation for both Flops are negative edge triggered
38:20 Question-2
38:42 Next Session
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Setup and Hold Time Requirement:
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